1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and, more particularly, to a method of manufacturing a high-frequency bipolar transistor required for a high-speed operation.
2. Description of the Related Art
In order to obtain good high-frequency characteristics in a high-frequency bipolar transistor required for a high-speed operation, an emitter having a long periphery is advantageous. In addition, a low base resistance and a small collector-base capacitance are preferred.
FIGS. 1A to 1C are sectional views sequentially showing conventional steps in manufacturing a high-frequency bipolar transistor. An n-type epitaxial layer 31 is formed on a silicon semiconductor substrate, elements of which are isolated, and a p-type base region 32 and a p+-type graft base region 33 implanted with a high-concentration p-type impurity and connected to the p-type base region 32 later are selectively formed in the epitaxial layer 31. The resultant structure is thermally oxidized to form a silicon oxide film 34, and then a silicon nitride film 35 is formed thereon (FIG. 1A).
In order to form an emitter region, the silicon nitride film 35 and the silicon thermal oxide film 34 on an area between the graft base regions 33 are partly removed by a photolithographic technique to form emitter contact holes 36. A polysilicon layer containing an n-type impurity is deposited on the entire surface of the resultant structure, and the resultant structure is patterned to form emitter electrodes 37. Thereafter, the n-type impurity contained in the polysilicon layer serving as the emitter electrode 37 is thermally diffused in the base region 32 by annealing to form an n-type emitter region 38 (FIG. 1B).
The silicon nitride film 35 and the silicon thermal oxide film 34 on the graft base region 33 are partly removed by a photolithographic technique to form base contact holes 39. Thereafter, an emitter electrode aluminum wiring layer 40 and a base electrode aluminum wiring layer 41 are patterned (FIG. 1C).
FIG. 2 is a plan view showing a pattern of the arrangement in FIG. 1C. The pattern is formed to have conditions for obtaining good high-frequency characteristics. That is, each of the emitter contact holes 36 is divided into a plurality of stripes so that an emitter has a long periphery. Therefore, base contact holes 39 are formed to put the corresponding emitter contact hole 36, therebelow to decrease base resistance.
In order to decrease the collector-base capacitance, base area must be decreased. As shown in FIG. 2, the emitter stripe has a width a and a pitch b which are set to be as small as possible.
However, as the pitch b of the emitter stripe is decreased, the interval between the emitter electrode aluminum wiring layer 40 and the base electrode aluminum wiring layer 41 is decreased. The margin for mask alignment using photolithographic etching becomes extremely decreased, making the emitter electrode and the base electrode easily short-circuited.
Thus, in accordance with the limitation due to the photolithographic technique, it is difficult when the pitch of the emitter stripe is decreased to a minimum line width, or less, because defects occur in the transistor.